1. Field of the Invention
The present invention relates to an integrated circuit and fabrication method. More specifically, the present invention relates to an integrated circuit including an interconnect structure connecting multiple vertical transistors with spacer gates.
2. Description of the Related Art
A key concept in the evolution of MOSFET integrated circuits is the usage of scaling to continually reduce the size of devices and thereby increase the density and speed of digital integrated circuits. The density of integrated circuits is improved by using smaller channel lengths and channel widths. The speed of digital integrated circuits is improved by increasing the saturation drain current I.sub.dsat of MOSFET devices, thereby promoting faster charging and discharging of parasitic capacitances. Fortunately, an increase in the saturation drain current I.sub.dsat of MOSFET devices automatically results from a decrease in channel length or a reduction in gate oxide thickness. In fact, models of MOSFET functionality imply that the saturation drain current I.sub.dsat will continue to increase indefinitely as the channel length and gate oxide thickness are reduced so that only limitations of process technology rather than device effects prevent the design and manufacture of ever smaller and increased performance MOSFETs.
The fabrication of increasingly smaller features in integrated circuits depends on the availability of increasingly higher resolution photolithography equipment. Increases in resolution have been gained by decreasing the illuminating wavelength of the optical equipment or increasing the numerical aperture of the system lens. Other techniques for increasing the resolution of photolithography equipment include increasing the contrast of the photoresist mask applied to the imaged semiconductor wafer. The contrast of the photoresist mask is increased by modifying the resist chemistry, creating entirely new photoresists, or using contrast enhancement layers to allow a smaller modulation transfer function to produce adequate images. Further enhancements are gained by adjusting the coherence of the optical system.
The need for high resolution lithography extends not only to the formation of integrated circuit devices but also to interconnect structures for electrically connecting the various devices. The formation of highly compact transistors and devices creates a problem of making connections with these transistors and devices. Typically interconnect structures are made through layers of oxide, forming an unsuitable, nonplanar structure. Interconnections to transistors and devices generally have a minimum feature size including structures for forming connections between portions of the integrated circuit. The minimum feature size limits the density of integrated circuit packing and circuit performance.
All of these techniques have been employed with varying degrees of success. However, further improvements in integrated circuit density and performance are continually sought.
What is needed is a technique for accurately and consistently creating smaller and increased performance MOSFETs and creating precise interconnect structures for connecting the smaller and increased performance MOSFETs.
What is further needed is a technique for making compact interconnections to compact transistors and devices.